adc10_a_ex7_repeatSingleDMA.c

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/* --COPYRIGHT--,BSD
 * Copyright (c) 2017, Texas Instruments Incorporated
 * All rights reserved.
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 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
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 *    from this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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#include "driverlib.h"
 
//******************************************************************************
//******************************************************************************
 
void main (void)
{
    uint16_t ADC_Result[64];
    volatile uint16_t ADC_Result_Average;
    uint8_t i;
    uint16_t ADC_Result_sum;
 
    //Stop Watchdog Timer
    WDT_A_hold(WDT_A_BASE);
 
    //Initialize the ADC10_A Module
    /*
     * Base Address for the ADC10_A Module
     * Use internal ADC10_A bit as sample/hold signal to start conversion
     * USE MODOSC 5MHZ Digital Oscillator as clock source
     * Use default clock divider of 1
     */
    ADC10_A_init(ADC10_A_BASE,
        ADC10_A_SAMPLEHOLDSOURCE_SC,
        ADC10_A_CLOCKSOURCE_ADC10OSC,
        ADC10_A_CLOCKDIVIDER_1);
 
    ADC10_A_enable(ADC10_A_BASE);
 
    /*
     * Base Address for the ADC10_A Module
     * Sample/hold for 16 clock cycles
     * Enable Multiple Sampling
     */
    ADC10_A_setupSamplingTimer(ADC10_A_BASE,
        ADC10_A_CYCLEHOLD_16_CYCLES,
        ADC10_A_MULTIPLESAMPLESENABLE);
 
    //Configure Memory Buffer
    /*
     * Base Address for the ADC10_A Module
     * Use input A1
     * Use positive reference of AVcc
     * Use negative reference of AVss
     */
    ADC10_A_configureMemory(ADC10_A_BASE,
        ADC10_A_INPUT_A1,
        ADC10_A_VREFPOS_AVCC,
        ADC10_A_VREFNEG_AVSS);
 
    //Initialize and Setup DMA Channel 0
    /*
     * Configure DMA channel 0
     * Configure channel for repeated single transfer
     * DMA interrupt flag will be set after every 64 transfers
     * Use DMA Trigger Source 24 (ADC10IFG)
     * Transfer Word-to-Word
     * Trigger upon Rising Edge of Trigger Source Signal
     */
    DMA_initParam param = {0};
    param.channelSelect = DMA_CHANNEL_0;
    param.transferModeSelect = DMA_TRANSFER_REPEATED_SINGLE;
    param.transferSize = 64;
    param.triggerSourceSelect = DMA_TRIGGERSOURCE_24;
    param.transferUnitSelect = DMA_SIZE_SRCWORD_DSTWORD;
    param.triggerTypeSelect = DMA_TRIGGER_RISINGEDGE;
    DMA_init(&param);
    /*
     * Configure DMA channel 0
     * Use ADC10_A Memory Buffer as source
     * Increment destination address after every transfer
     */
    DMA_setSrcAddress(DMA_CHANNEL_0,
        ADC10_A_getMemoryAddressForDMA(ADC10_A_BASE),
        DMA_DIRECTION_UNCHANGED);
    /*
     * Base Address for the DMA Module
     * Configure DMA channel 0
     * Use ADC_Result[0] as destination
     * Increment destination address after every transfer
     */
    DMA_setDstAddress(DMA_CHANNEL_0,
        (uint32_t)(uintptr_t)&ADC_Result[0],
        DMA_DIRECTION_INCREMENT);
 
    //Enable DMA channel 0 interrupt
    DMA_clearInterrupt(DMA_CHANNEL_0);
    DMA_enableInterrupt(DMA_CHANNEL_0);
 
    //Enable transfers on DMA channel 0
    DMA_enableTransfers(DMA_CHANNEL_0);
 
    while (1)
    {
        //Enable and Start the conversion
        //in Repeated Single-Channel Conversion Mode
        ADC10_A_startConversion(ADC10_A_BASE,
            ADC10_A_REPEATED_SINGLECHANNEL);
 
        __bis_SR_register(CPUOFF + GIE);        //LPM0, ADC10_A_ISR will force exit
        __no_operation();                       //For debug only
 
        //Clear accumulate register
        ADC_Result_sum = 0x0;
        for (i = 0; i < 64; i++){
            ADC_Result_sum += ADC_Result[i];
        }
 
        //Average of 64 conversions results
        ADC_Result_Average = ADC_Result_sum >> 6;
 
        //SET BREAKPOINT HERE to be able to watch ADC_Result_Average
        //Delay before next 64 conversions
        __delay_cycles(50000);
    }
}
 
 
// DMA interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
__interrupt
#elif defined(__GNUC__)
__attribute__((interrupt(DMA_VECTOR)))
#endif
void DMA0_ISR (void) {
    switch (__even_in_range(DMAIV,16)){
        case  0: break; //No interrupt
        case  2:        //DMA0IFG
            //64 conversions complete
            //Disable Conversions without pre-empting any conversions taking place.
            ADC10_A_disableConversions(ADC10_A_BASE,
            ADC10_A_PREEMPTCONVERSION);
            //Exit LPM
            __bic_SR_register_on_exit(CPUOFF);
            break;
        case  4: break; //DMA1IFG
        case  6: break; //DMA2IFG
        default: break;
    }
}